Computer Architecture For Parallel Paradigms

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Mostrando 121 - 150 resultados de 228

2011

From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype

The 7th International Symposium on Applied Reconfigurable Computing (ARC 2011)

N. Sönmez, O. Arcas, G. Sayilar, A. Cristal, I. Hur, O. Unsal, S. Singh, and M. Valero
Circuit Design of a Dual-Versioning L1 Data Cache

Integration The VLSI Journal

A. Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur, and M. Valero
TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System

The 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011)

N. Sönmez, O. Arcas, O. Pflucker, A. Cristal, O. Unsal, I. Hur, S. Singh, and M. Valero

2010

The Velox Transactional Memory Stack

Micro, IEEE

P. Felber, E. Rivière, W. M. Moreira, D. Harmanci, P. Marlier, S. Diestelhorst, M. Hohmuth, M. Pohlack, A. Cristal, I. Hur, O. Unsal, P. Stenström, A. Dragojevic, R. Guerraoui, M. Kapalka, V. Gramoli, U. Drepper, S. Tomić, Y. Afek, G. Korland, N. Shavit, C. Fetzer, M. Nowack, and T. Riegel
ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance

A. Armejach, A. Seyedi, R T. J. Gil, I. Hur, O. Unsal, A. Cristal, and M. Valero
Architectural Support for Fair Reader-Writer Locking

International Symposium on Microarchitecture

E. Vallejo, R. Beivide, A. Cristal, T. Harris, F. Vallejo, O. Unsal, and M. Valero
RMS-TM: A challenging transactional memory benchmark suite

Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2010)

V. Karakostas, G. Kestor, O. Unsal, A. Cristal, I. Hur, and M. Valero
FaulTM: Fault-Tolerance Using Hardware Transactional Memory

Workshop on Parallel Execution of Sequential Programs on Multi-core Architecture (PESPMA)

G. Yalcin, O. Unsal, I. Hur, and A. Cristal
Transactiﬁcation of a real-world system library

5th ACM SIGPLAN Workshop on Transactional Computing - TRANSACT 2010

N. Miletić, V. Smiljkovic, C. Perfumo, T. Harris, A. Cristal, I. Hur, O. Unsal, and M. Valero
Dynamic Filtering: Multi-Purpose Architecture Support for Language Runtime Systems

5th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'10)

T. Harris, S. Tomić, A. Cristal, and O. Unsal
Debugging Programs that use Atomic Blocks and Transactional Memory

15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP 2010)

F. Zyulkyarov, T. Harris, O. Unsal, A. Cristal, and M. Valero

2009

Taking the heat off transactions: Dynamic selection of pessimistic concurrency control

Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing

N. Sonmez, T. Harris, A. Cristal, O. Unsal, and M. Valero
QuakeTM: parallelizing a complex sequential application using transactional memory

Proceedings of the 23rd international conference on Supercomputing

V. Gajinov, F. Zyulkyarov, O. Unsal, A. Cristal, E. Ayguade, T. Harris, and M. Valero
EazyHTM: eager-lazy hardware transactional memory

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture

S. Tomić, C. Perfumo, C. Kulkarni, A. Armejach, A. Cristal, O. Unsal, T. Harris, and M. Valero
Content Aware Architectures

R. González
Architecture for Object-Oriented Programming Model

N. Markovic, R. González, O. Unsal, M. Valero, and A. Cristal
EazyHTM, Eager-Lazy Hardware Transactional Memory

42nd International Symposium on Microarchitecture (MICRO)

S. Tomić, C. Perfumo, C. Kulkarni, A. Armejach, A. Cristal, O. Unsal, T. Harris, and M. Valero
Software Transactional Memory Implementation

Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2009)

N. Sönmez, C. Perfumo, S. Stipić, T. Harris, O. Unsal, A. Cristal, and M. Valero
QuakeTM: parallelizing a complex sequential application using transactional memory

23rd international conference on Supercomputing (ICS 2009)

V. Gajinov, F. Zyulkyarov, O. Unsal, A. Cristal, E. Ayguade, T. Harris, and M. Valero
Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory

11th IEEE International Conference on High Performance Computing and Communications, HPCC 2009

S. Sanyal, S. Roy, A. Cristal, O. Unsal, and M. Valero
Clock gate on abort: Towards energy-efficient hardware Transactional Memory

23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009)

S. Sanyal, S. Roy, A. Cristal, O. Unsal, and M. Valero
Profiling Transactional Memory applications on an Atomic Block Basis: A Haskell case study

Second Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG 2009)

N. Sönmez, A. Cristal, O. Unsal, T. Harris, and M. Valero
Taking the heat off transactions: Dynamic selection of pessimistic concurrency control

23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009)

N. Sönmez, T. Harris, A. Cristal, O. Unsal, and M. Valero
RMS-TM: A Transactional Memory Benchmark for Recognition, Mining and Synthesis Applications

4th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2009)

G. Kestor, S. Stipić, O. Unsal, A. Cristal, and M. Valero
Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions

14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009)

C. Kulkarni, O. Unsal, A. Cristal, E. Ayguade, and M. Valero
Atomic Quake: Using Transactional Memory in an Interactive Multiplayer Game Server

14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009)

F. Zyulkyarov, V. Gajinov, O. Unsal, A. Cristal, E. Ayguade, T. Harris, and M. Valero
Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions

ACM SIGPLAN Notices

C. Kulkarni, O. Unsal, A. Cristal, E. Ayguade, and M. Valero

2008

The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment

Computing Frontiers '08

C. Perfumo, N. Sönmez, S. Stipic, O. Unsal, A. Cristal, T. Harris, and M. Valero
A distributed processor state management architecture for large-window processors

41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41)

I. González, M. Galluzzi, A. Veidenbaum, A. Ramirez, A. Cristal, and M. Valero
Affordable kilo-instruction processors

M. Pericas

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