Lagarto HUN (Lagarto 1)

Cores RISC-V Hardware

Lagarto Hun is a segmented scalar processor with in-order execution using the RISC-V open-source instruction set.

In collaboration between BSC and CIC-IPN, originally Lagarto Hun was a RV64IMA core with a 5-stage pipeline in order, supporting privileged ISA v1.11. As a first improvement, we have added support for single and double precision floating point operations, becoming Lagarto Hun into a RV64GCV + (subset RVV0.7.1) core, commonly named as RV64G for general purpose core. 

It may be used for embedded systems and education.

Software Author: 
Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J,Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, Victor Jiménez, Leonidas Kosmidis, Vatistas Kostablabros, Rubén Langarita, Guillem López-Paradis, Joan Marimon, Jonnatan Mendoza, Miquel Moretó, Julián Pavón, Cristóbal Ramírez, Carlos Rojas, Abraham Ruiz, Nehir Sonmez, Victor Soria, Osman Unsal, Mateo Valero, Iván Vargas
Contacto:
License: 

Solderpad Hardware License

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