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2008

A Distributed Processor State Management Architecture for Large-Window Processors

I. González, M. Galluzzi, A. Veidenbaum, M. A. Ramírez, A. Cristal, and M. Valero
A distributed processor state management architecture for large-window processors

41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41)

I. González, M. Galluzzi, A. Veidenbaum, M. A. Ramírez, A. Cristal, and M. Valero

2007

Low power instructions issue queue design for out of order processors

M. A. Ramírez

2005

A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation

IEEE International Conference on Computer Design (ICCD-2005)

M. A. Ramírez, A. Cristal, M. Valero, A. Veidenbaum, and L. A. Villa

2004

INSTRUCTION WAKEUP MECHANISM: Power and Timing Evaluation

CIC,s Research and Computing Science

M. A. Ramírez, A. Cristal, L. A. Villa, A. Veidenbaum, and M. Valero
Direct Instruction Wakeup for OOO processors

Innovative Architecture for Future Generation High-Performance Processors and System

M. A. Ramírez, A. Cristal, L. A. Villa, A. Veidenbaum, and M. Valero
A partitioned instruction queue to reduce instruction wakeup energy

International Journal of High Performance Computing and Networking

M. A. Ramírez, A. Cristal, M. Valero, A. Veidenbaum, and L. A. Villa

2003

A Simple Low-Energy Instruction Wakeup Mechanism

5th International Symposium on High Performance Computing (ISHPC-V)

M. A. Ramírez, A. Cristal, A. Veidenbaum, L. A. Villa, and M. Valero
A Low-Power-Instruction-Queue Wakeup Mechanism

XIV Jornadas de Paralelismo

M. A. Ramírez, A. Cristal, A. Veidenbaum, L. A. Villa, and M. Valero