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2003

Tolerating branch predictor latency on SMT

5th International Symposium on High Performance Computing (ISHPC-V)

A. Falcón, O. J. Santana, A. Ramirez, and M. Valero
An Analysis of Dynamic Instruction Streams

XIV Jornadas de Paralelismo

O. J. Santana, M. Galluzzi, A. Ramirez, and M. Valero
Latency Tolerant Branch Predictors

2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03)

O. J. Santana, A. Ramirez, and M. Valero
Improving Memory Latency Aware Fetch Policies for SMT Processors

5th International Symposium on High Performance Computing (ISHPC-V)

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero
CDE: A Compiler-driven, Dependence-Centric, Eager-executing Architecture for the Billion Transistors Era

Workshop on Complexity-Effective Design (WCED 2003)

C. Acosta, S. Vajapeyam, A. Ramirez, and M. Valero
Dealing with Billions of Transistors

XIV Jornadas de Paralelismo

C. Acosta, M. Galluzzi, S. Vajapeyam, A. Ramirez, and M. Valero
Application/Kernel Cooperation Towards the Efficient Execution of Shared-memory Parallel Java Codes

17th IEEE International Parallel and Distributed Processing Symposium (IPDPS'03)

J. Guitart, X. Martorell, J. Torres, and E. Ayguade
Complete Instrumentation Requirements for Performance Analysis of Web based Technologies

IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'03)

D. Carrera, J. Guitart, J. Torres, E. Ayguade, and J. Labarta

2002

Large Virtual ROBs by Processor Checkpointing

A. Cristal, M. Valero, A. González, and J. Llosa
ROBs Virtuales utilizando checkpoints

XIII Jornadas de Paralelismo

A. Cristal, and M. Valero

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