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2004

A clustered Processor based on Content-Aware Register File

R. González, A. Cristal, A. Veidenbaum, M. Pericas, and M. Valero
INSTRUCTION WAKEUP MECHANISM: Power and Timing Evaluation

CIC,s Research and Computing Science

M. A. Ramírez, A. Cristal, L. A. Villa, A. Veidenbaum, and M. Valero
An Optimized Front-End Physical Register File with Banking and Writeback Filtering

Workshop on Power-Aware Computer Systems (PACS'04)

M. Pericas, R. González, A. Cristal, A. Veidenbaum, and M. Valero
Maintaining Thousands of In-Flight Instructions

10th International Euro-Par 2004 Conference

A. Cristal, O. J. Santana, and M. Valero
A Content Aware Integer Register File Organization

International Symposium on Computer Architecture (ISCA 2004)

R. González, A. Cristal, D. Ortega, A. Veidenbaum, and M. Valero
Scalable Distributed Register File

5th Workshop on Complexity-Effective Design

R. González, A. Cristal, M. Pericas, A. Veidenbaum, and M. Valero
Evaluating Kilo-instruction Multiprocessors

3rd Workshop on Memory Performance Issues (WMPI-2004)

M. Galluzzi, V. Puente, A. Cristal, R. Beivide, J. A. G. Monasterio, and M. Valero
A Comprehensive Description of Kilo-Instruction Processors

5o Congreso Nacional de Computación

A. Cristal, O. J. Santana, and M. Valero
Out-of-Order Commit Processors

10th International Symposium on High Performance Computer Architecture (HPCA-10)

A. Cristal, D. Ortega, J. Llosa, and M. Valero
Direct Instruction Wakeup for OOO processors

Innovative Architecture for Future Generation High-Performance Processors and System

M. A. Ramírez, A. Cristal, L. A. Villa, A. Veidenbaum, and M. Valero

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