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2006

Analysis of multithreading capabilities of current high-performance processors

K. Kedzierski, F. Cazorla, and M. Valero
Improving EDF for SMT processors

C. Boneti, F. Cazorla, and M. Valero
Implementando recuperaciones precisas en procesadores con consolidación fuera de orden

I. González, O. J. Santana, A. Pajuelo, and M. Valero
Microarchitectural Support for Speculative Register Renaming

J. J. Alastruey, T. Monreal, V. Viñals, and M. Valero
Kilo-instruction Processors, Runahead and Prefetching

T. Ramírez, M. Pajuelo, O. J. Santana, and M. Valero
Speculative Early Register Release

J. J. Alastruey, T. Monreal, V. Viñals, and M. Valero
Branch Predictor Guided Instruction Decoding

IEEE Intl. Conference on Parallel Architectures and Compiler Techniques (PACT-2006)

O. J. Santana, A. Falcón, A. Ramirez, and M. Valero
Fast Speculative Address generation and Way Caching for Reducing L1 data Cache Energy

B. Slamat, D. Nicolaescu, A. Veidenbaum, and M. Valero
A Simple Speculative Load Control Mechanism for Energy Saving

T. Ramírez, M. Pajuelo, O. J. Santana, and M. Valero
Performance Analysis of Sequence Alignment Applications

IISWC, IEEE Internacional Symposium on Workload Characterization

F. Sánchez, E. Salami, A. Ramirez, and M. Valero

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