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2002

A comparative study of redundancy in trace caches

Intl. Euro-Par Conference

H. Vandierendonck, A. Ramirez, K D. Bosschere, and M. Valero
Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures

International Workshop on Innovative Architecture (IWIA 2002)

P. Knijnenburg, A. Ramirez, F. Latorre, J. Lluis Larriba-Pey, and M. Valero
Mesocode: Optimizations for Improving Fetch Bandwidth of Itanium Processors

Workshop on Complexity-Effective Design

M. Eng, H. Wang, P. Wang, A. Ramirez, J. Fung, and J. Shen
A Comprehensive Analysis of Indirect Branch Prediction

4th International Symposium on High Performance Computing (ISHPC-4)

O. J. Santana, A. Falcón, E. Fernández, P. Medina, A. Ramirez, and M. Valero
Studying New Ways for Improving Adaptive History Length Branch Predictors

4th International Symposium on High Performance Computing (ISHPC-4)

A. Falcón, O. J. Santana, P. Medina, E. Fernández, A. Ramirez, and M. Valero
Fetching Instruction Streams

35th Annual International Symposium on Microarchitecture (MICRO-35)

A. Ramirez, O. J. Santana, J. Lluis Larriba-Pey, and M. Valero
Software Trace Cache for Commercial Applications

International Journal of Parallel Programming

A. Ramirez, J. Lluis Larriba-Pey, C. Navarro, M. Valero, and J. Torrellas
Branch classification for SMT fetch gating

6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC6)

P. Knijnenburg, A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Analisis y caracterización de los bucles

XIII Jornadas de Paralelismo

A. García, E. Fernández, P. Medina, A. Ramirez, and M. Valero
Estudio y evaluación de mecanismos de control de la Especulación

In XIII Jornadas de Paralelismo, Lleida (Spain)

F. Cazorla, P. Medina, E. Fernández, A. Ramirez, and M. Valero

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