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2004

Traffic Aggregation Impact on the Memory Performance of Networking Applications

J. Verdú, M. Nemirovsky, J. García, and M. Valero
Analysis of Traffic Traces for Stateful Applications

J. Verdú, J. García, M. Nemirovsky, and M. Valero
Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers

M. March, J. García, L.. Cerdá, and M. Valero
A Hybrid DRAM/SRAM Design for Fast Packet Buffers

J. García, M. March, L.. Cerdá, J. Corbal, and M. Valero
Heterogeneity-Aware Architectures

XV Jornadas de Paralelismo

C. Acosta, A. Falcón, A. Ramirez, and M. Valero
Prophet/Critic Hybrid Branch Prediction

31st Annual International Symposium on Computer Architecture (ISCA-31)

A. Falcón, J. Stark, A. Ramirez, K. Lai, and M. Valero
Approaching a Smart Sharing of Resources in SMT Processors

Workshop on Complexity-Effective Design (WCED)

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero
A Complexity-Effective Decoding Architecture Based on Instruction Streams

Workshop on Complexity-Effective Design (WCED)

O. J. Santana, A. Falcón, A. Ramirez, and M. Valero
Implicit vs. Explicit Resource Allocation in SMT Processors

2004 Euromicro Symposium on Digital Systems Design (DSD 2004)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors

10th International Conference on High Performance Computer Architecture (HPCA-10)

A. Falcón, A. Ramirez, and M. Valero

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