Computer Architecture - Operating Systems (CAOS)

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Mostrando 271 - 298 resultados de 298

2008

Virtual Private Machines: Hardware/Software Interactions in the Multicore Era

K. J. Nesbit, M. Moreto, F. Cazorla, A. Ramirez, M. Valero, and J. E. Smith

2007

Measuring the Performance of Multithreaded Processors

J. Vera, F. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández, and M. Valero
On the Problem of Minimizing Workload Execution Time in SMT Processors

International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
Online Prediction of Throughput for Different Cache Sizes

XVIII Jornadas de Paralelismo

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
MLP-aware dynamic cache partitioning

International Conference on Parallel Architectures and Compilation Techniques (PACT)

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
Explaining Dynamic Cache Partitioning Speed Ups

IEEE Computer Architecture Letters

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
Online Prediction of Applications Cache Utility

International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS)

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors

1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007)

C. Acosta, F. Cazorla, A. Ramirez, and M. Valero

2006

A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures

J. Vera, F. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández, and M. Valero
Predictable Performance in SMT processors: Synergy Between the OS and SMTs

IEEE Transactions on Computers

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero

2005

Kilo-instruction Processors: Overcoming the Memory Wall

IEEE Micro

A. Cristal, O. J. Santana, F. Cazorla, M. Galluzzi, T. Ramírez, M. Pericas, and M. Valero
Quality of service for Simultaneous Multithreading Processors

ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems

F. Cazorla, P. Knijnenburg, R. Sakellarious, E. Fernández, A. Ramirez, and M. Valero
Dynamically Controlled Resource Allocation in SMT

XVI Jornadas de Paralelismo. Granada

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero
Metrics for the Evaluation of SMT Processors Performance

XVI Jornadas de Paralelismo

S. Mir, F. Cazorla, A. Ramirez, and M. Valero
Architectural Support for Real-Time Task Scheduling in SMT Processors

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero

2004

Feasibility of QoS for SMT by Resource Allocation.

Lecture Notes in Computer Science (LNCS)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
Enabling SMT for Real-Time Embedded Systems.

European Signal Processing Conference (EUSIPCO)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
Implicit vs. Explicit Resource Allocation in SMT Processors

2004 Euromicro Symposium on Digital Systems Design (DSD 2004)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors

International Journal of High Performance Computing and Networking (IJHPCN)

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero
DCache Warn: An I-Fetch Policy To Increase SMT Efficiency

18th International Parallel and Distributed Processing Symposium (IPDPS-2004)

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero
Dynamically Controlled Resource Allocation in SMT Processors

37th Annual International Symposium on Microarchitecture (MICRO-37)

F. Cazorla, A. Ramirez, M. Valero, and E. Fernández
QoS for High-Performance SMT Processors in Embedded Systems

IEEE Micro

F. Cazorla, A. Ramirez, M. Valero, P. Knijnenburg, R. Sakellariou, and E. Fernández
Predictable Performance in SMT Processors

Computing Frontiers (CF'04)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
Throughput versus Quality of Service in SMT processors

Euromicro-DSD (Digital System Design)

E. Fernández, F. Cazorla, A. Ramirez, P. Knijnenburg, R. Sakellariou, and M. Valero
Approaching a Smart Sharing of Resources in SMT Processors

Workshop on Complexity-Effective Design (WCED)

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero

2003

Improving Memory Latency Aware Fetch Policies for SMT Processors

5th International Symposium on High Performance Computing (ISHPC-V)

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero

2002

Estudio y evaluación de mecanismos de control de la Especulación

In XIII Jornadas de Paralelismo, Lleida (Spain)

F. Cazorla, P. Medina, E. Fernández, A. Ramirez, and M. Valero

"SafeLS: Toward Building a Lockstep NOEL-V Core" (to appear)

M. Sarraseca, S. Alcaide, F. Fuentes, J. Carlos Rodriguez, F. Chang, I. Lasfar, R. Canal, F. J. Cazorla, and J. Abella

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