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2005

Architectural Support for Real-Time Task Scheduling in SMT Processors

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
Software Trace Cache

IEEE Transactions on Computers

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Better branch prediction through prophet/critic hybrids

IEEE Micro

A. Falcón, J. Stark, A. Ramirez, K. Lai, and M. Valero
hdSMT: An Heterogeneity-Aware Simultaneous Multithreaded Architecture

XVI Jornadas de Paralelismo

C. Acosta, A. Falcón, A. Ramirez, and M. Valero
Hierarchical Topologies for Large-Scale Two-Level Networks

M. Moreto, C. Martínez, E. Vallejo, M. Beivide, and M. Valero
Dynamically Controlled Resource Allocation in SMT

XVI Jornadas de Paralelismo. Granada

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero
Workload Analysis of Networking Applications

J. Verdú, M. Nemirovsky, J. García, and M. Valero
Metrics for the Evaluation of SMT Processors Performance

XVI Jornadas de Paralelismo

S. Mir, F. Cazorla, A. Ramirez, and M. Valero
Predicting two Streams per Cycle

XVI Jornadas de Paralelismo

O. J. Santana, A. Ramirez, and M. Valero
Multiple Stream Prediction

ISHPC. International Symposium on High Performance Computers

O. J. Santana, A. Ramirez, and M. Valero

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