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Guide to design on a single FPGA

This section describes the steps required for a design based on a compiling Lagarto Ka RISC-V core, compiled with FPGA MEEP Shell.

Set up the Environment​

  1. Copy the design to the local storage:
$ git clone https://gitlab.bsc.es/meep/FPGA_implementations/AlveoU280/fpga_shell.git -b production
$ cd fpga_shell
$ make initialize LOAD_EA=kameleon
  1. Add RISC-V toolchain PATH to your environment:
export RISCV=/home/tools/riscv_vector_toolchain/rvv-0.7.1/bin/
export PATH=$PATH:$RISCV
  1. Specify Vivado to version 2021.2, changing your PATH:
export PATH=$PATH:/opt/Xilinx/Vivado/2021.2/bin/
export PATH=<parentpath>/qdma_drivers_linux/bin:$PATH

Build Linux Binaries​

  1. Linux Boot (optional): You can generate all the RISC-V tool flow and a linux image, but it may take long:
$ make binaries

Binary of the Linux Boot: fw_payload.bin

  1. Bootrom: You can only generate the bootrom:
$ mkdir -p binaries
$ make -C accelerator/sw/bootrom_uart/apps
$ cp -r accelerator/meep_shell/binaries/* binaries
$ cp accelerator/sw/bootrom_uart/apps/boot.hex accelerator/meep_shell/binaries/initrom.mem

Compile the Design and Generate Bitstream​

  1. Non-GUI mode: By default, the project build will activate the Sargantana core. For generating the bitstream on command line:
$ make project
$ make bitstream

The generated bitstream will be located on bitstream/system.bit

  1. GUI mode: For generating the bitstream with GUI:
$ make project
$ vivado

Inside the GUI, open the project located on project/system.xpr, and inside you can generate the bitstream. The generated bitstream will be located on project/system.runs/impl_1/system.bit by default.

Program the FPGA and Boot Linux​

  1. Clone fpga-tools repo and compile PCIe driver:
$ git clone --recursive https://gitlab.bsc.es/meep/FPGA_implementations/AlveoU280/fpga-tools.git
$ cd ./fpga-tools/fpga
$ ./build_pcie_drivers.sh

Note: Choose an FPGA board number: After login at the FPGA Cluster node a welcome screen shows a table with the boards (1-8).To load bitstreams on the Alveo FPGAs, there is a custom script that handles the whole process, from loading the bistream to setting up the necessary PCIe configuration to use it.

  1. Load the bitstream into the FPGA:
  • To load bistreams that use the Xilinx QDMA IP:
./load-bitstream-onic.sh qdma <your_bitstream_here>.bit <board-number>
  • To load bistreams that use the Xilinx XDMA IP:
./load-bitstream-onic.sh xdma <your_bitstream_here>.bit <board-number>

The bitstream will be programmed in the FPGA and the Xilinx PCIe API.

  1. Bring up Onic driver:
  • Activate the onic driver:
./load-bitstream-onic.sh driverup <board-number>
  • Deactivate the ONIC driver:
./load-bitstream-onic.sh driverdown <board-number>
  1. Boot a Fedora image: It is necessary to have the fedora image and an opensbi binary (See Step 2). You can use the following steps to load the bistream and load the fedora image and opensbi.bin all at once.
./load-bitstream-onic-nfs.sh qdma <your_bitstream_here>.bit
./load-bitstream-onic-nfs.sh x--reload-fs <your_fedora_image.img> <your_osbi.bin>
  1. Open the UART port to the host in another terminal tab:
  • With screen:
$ screen /dev/ttyUSB2 115200
  • With picocom:
$ picocom -b 115200 -r -l --imap=lfcrlf /dev/ttyUSB2

You can check the UART output log when you boot any binary. This is the way to use the fpga_test.sh script:

./fpga_test.sh <output_file.log> <"String">