Publications

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2007

HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications

2007 IEEE International Symposium on Workload Characterization (IISWC-2007)

M. Álvarez, E. Salami, A. Ramirez, and M. Valero
Enlarging Instruction Streams

IEEE Transactions on Computers

O. J. Santana, A. Ramirez, and M. Valero
On the Problem of Minimizing Workload Execution Time in SMT Processors

International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
FAME: FAirly MEasuring Multithreaded Architectures

J. Vera, F. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández, and M. Valero
Online Prediction of Throughput for Different Cache Sizes

XVIII Jornadas de Paralelismo

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
MLP-aware dynamic cache partitioning

International Conference on Parallel Architectures and Compilation Techniques (PACT)

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
Explaining Dynamic Cache Partitioning Speed Ups

IEEE Computer Architecture Letters

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
Online Prediction of Applications Cache Utility

International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS)

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors

1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007)

C. Acosta, F. Cazorla, A. Ramirez, and M. Valero
Performance Impact of the Interconnection Network on MareNostrum Applications

1st Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2007)

A. Ramirez, O. Prat, J. Labarta, and M. Valero

Pages