News & Publications

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News

RNE
Monday, 11 June, 2018
El BSC en el programa L'altra radio de RNE
La Verdad
Tuesday, 5 June, 2018
«Las recetas de cocina no son sino algoritmos culturales»
ABC
Tuesday, 29 May, 2018
México condecora al director del BSC con la máxima distinción a un extranjero
La Vanguardia
Tuesday, 29 May, 2018
México condecora al director del BSC con la máxima distinción a un extranjero
EEEnews Embedded
Thursday, 10 May, 2018
RISC-V has Supercomputer powers
BSC
Friday, 20 April, 2018
The Government of Mexico grants the Decoration of the Mexican Order of the Aztec Eagle to the director of the BSC
The director of the Barcelona Supercomputing Center (BSC) will receive the award of the Mexican Order of the Aztec Eagle in degree of insignia by the Mexican government. The Order of the Aztec Eagle is part of the Mexican Honours System and it is the highest Mexican order awarded to foreigners...
BSC
Friday, 20 April, 2018
The Government of Mexico grants the Decoration of the Mexican Order of the Aztec Eagle to the director of the BSC
The director of the Barcelona Supercomputing Center (BSC) will receive the award of the Mexican Order of the Aztec Eagle in degree of insignia by the Mexican government. The Order of the Aztec Eagle is part of the Mexican Honours System and it is the highest Mexican order awarded to foreigners...
BSC
Friday, 20 April, 2018
The Government of Mexico grants the Decoration of the Mexican Order of the Aztec Eagle to the director of the BSC
The director of the Barcelona Supercomputing Center (BSC) will receive the award of the Mexican Order of the Aztec Eagle in degree of insignia by the Mexican government. The Order of the Aztec Eagle is part of the Mexican Honours System and it is the highest Mexican order awarded to foreigners...
BSC
Friday, 20 April, 2018
The Government of Mexico grants the Decoration of the Mexican Order of the Aztec Eagle to the director of the BSC
The director of the Barcelona Supercomputing Center (BSC) will receive the award of the Mexican Order of the Aztec Eagle in degree of insignia by the Mexican government. The Order of the Aztec Eagle is part of the Mexican Honours System and it is the highest Mexican order awarded to foreigners...
BSC
Friday, 20 April, 2018
The Government of Mexico grants the Decoration of the Mexican Order of the Aztec Eagle to the director of the BSC
The director of the Barcelona Supercomputing Center (BSC) will receive the award of the Mexican Order of the Aztec Eagle in degree of insignia by the Mexican government. The Order of the Aztec Eagle is part of the Mexican Honours System and it is the highest Mexican order awarded to foreigners...

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Publications

V. Dimić, Moreto, M., Casas, M., Ciesko, J., and Valero, M., “RICH: Implementing Reductions in the Cache Hierarchy”, Proceedings of the 34th ACM International Conference on Supercomputing (ICS'20). pp. 1 - 13, 2020.
C. Ortega, Garcia, V., Moreto, M., Casas, M., and Rusitoru, R., “Data Prefetching on In-order Processors”, 2018 International Conference on High Performance Computing & Simulation (HPCS). pp. 322 - 329, 2018.
I. Pietri, Zhuang, S., Casas, M., Moreto, M., and Sakellariou, R., “Evaluating Scientific Workflow Execution on an Asymmetric Multicore Processor”, Lecture Notes in Computer ScienceEuro-Par 2017: Parallel Processing Workshops, vol. 10659. pp. 439 - 451, 2018.
I. Sánchez-Barrera, Moreto, M., Ayguadé, E., Labarta, J., Valero, M., and Casas, M., “Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies”, Proceedings of the 2018 International Conference on Supercomputing - ICS '18. pp. 207 - 217, 2018.
P. Caheny, Alvarez, L., Valero, M., Moreto, M., and Casas, M., “Runtime-assisted Cache Coherence Deactivation in Task Parallel Programs”, Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC). Piscataway, NJ, USA, pp. 35:1–35:12, 2018.
L. Alvarez, Casas, M., Labarta, J., Ayguadé, E., Valero, M., and Moreto, M., “Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs”, Proceedings of the 2018 International Conference on Supercomputing - ICS '18. pp. 218 - 228, 2018.
I. Brumar, Casas, M., Moreto, M., Valero, M., and Sohi, G. S., “ATM: Approximate Task Memoization in the Runtime System”, 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS). Orlando, FL, USA, pp. 1140 - 1150, 2017.
X. Tan, Bosch, J., Vidal, M., Álvarez, C., Jiménez-González, D., Ayguade, E., and Valero, M., “General Purpose Task-Dependence Management Hardware for Task-Based Dataflow Programming Models”, 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS). pp. 244 - 253, 2017.
C. Ortega, Moreto, M., Casas, M., Bertran, R., Buyuktosunoglu, A., Eichenberger, A. E., and Bose, P., “libPRISM: An Intelligent Adaption of Prefetch and SMT Levels”, Proceedings of the 31st ACM International Conference on Supercomputing (ICS). 2017.
V. Dimić, Moreto, M., Casas, M., and Valero, M., “Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals”, Lecture Notes in Computer ScienceEuro-Par 2017: Parallel Processing, vol. 10417. pp. 247 - 259, 2017.
E. Stafford, Pérez, B., Bosque, J. Luis, Beivide, R., and Valero, M., “To Distribute or Not to Distribute: The Question of Load Balancing for Performance or Energy”, Lecture Notes in Computer ScienceEuro-Par 2017: Parallel Processing, vol. 10417. pp. 710 - 722, 2017.
M. Stanic, Palomar, O., Hayes, T., Ratković, I., Cristal, A., Ünsal, O., and Valero, M., “An Integrated Vector-Scalar Design on an In-Order ARM Core”, ACM Transactions on Architecture and Code Optimization, vol. 14. pp. 1 - 26, 2017.
M. Stanic, Palomar, O., Hayes, T., Ratković, I., Cristal, A., Ünsal, O., and Valero, M., “An Integrated Vector-Scalar Design on an In-Order ARM Core”, ACM Transactions on Architecture and Code Optimization, vol. 14. pp. 1 - 26, 2017.
M. Casas and Bronevetsky, G., “Prediction of the impact of network switch utilization on application performance via active measurement”, Parallel Computing, vol. 67. pp. 38 - 56, 2017.
K. Chronaki, Rico, A., Casas, M., Moreto, M., Badia, R. M., Ayguadé, E., Labarta, J., and Valero, M., “Task scheduling techniques for asymmetric multi-core systems”, IEEE Transactions on Parallel and Distributed Systems , vol. 28. IEEE, pp. 2074-2087, 2017.
E. Castillo, Moreto, M., Casas, M., Alvarez, L., Vallejo, E., Chronaki, K., Badia, R. M., Bosque, J. Luis, Beivide, R., Ayguade, E., Labarta, J., and Valero, M., “CATA: Criticality Aware Task Acceleration for Multicore Processors”, 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, Chicago, IL, USA, pp. 413-422, 2016.
T. Hayes, Palomar, O., Unsal, O., Cristal, A., and Valero, M., “Future Vector Microprocessor Extensions for Data Aggregations”, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). IEEE, Seoul, South Korea, pp. 418-430, 2016.
T. Grass, Allande, C., Armejach, A., Rico, A., Ayguade, E., Labarta, J., Valero, M., Casas, M., and Moreto, M., “MUSA: A Multi-level Simulation Approach for Next-generation HPC Machines”, Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis. Salt Lake City, Utah, pp. 45:1–45:12, 2016.
X. Tan, Bosch, J., Jiménez-González, D., Alvarez-Martinez, C., Ayguade, E., and Valero, M., “Performance analysis of a hardware accelerator of dependence management for task-based dataflow programming models”, 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). IEEE, Uppsala, Sweden, pp. 225 - 234, 2016.
K. Chronaki, Moreto, M., Casas, M., Rico, A., Badia, R. M., Ayguade, E., Labarta, J., and Valero, M., “POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware”, Proceedings of the 2016 International Conference on Parallel Architectures and Compilation - PACT '16. Haifa, Israel , pp. 415 - 417, 2016.

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