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2001

Code Layout Optimizations for Transaction Processing Workloads

28th Annual International Symposium on Computer Architecture (ISCA-28)

A. Ramirez, L. A. Barroso, K. Gharachorloo, R. Cohn, J. Lluis Larriba-Pey, G. Lowney, and M. Valero
Instruction Fetch Architectures and Code Layout Optimizations

Proceedings of the IEEE

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
An In-Depth Evaluation of the Multi-Stage Cascaded Predictor

XII Jornadas de Paralelismo, Valencia (Spain)

O. J. Santana, A. Falcón, E. Fernández, P. Medina, A. Ramirez, and M. Valero
An Analysis of Dynamic History Length Fitting

XII Jornadas de Paralelismo, Valencia (Spain)

A. Falcón, O. J. Santana, P. Medina, E. Fernández, A. Ramirez, and M. Valero
Branch Prediction Using Profile Data

7th International Euro-Par Conference (Euro-Par'2001)

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero

2000

A Stream Processor Front-end

IEEE Technical Committee on Computer Architecture Newsletter

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
The Effect of Code Reordering on Branch Prediction

International Conference on Parallel Architectures and Compilation Techniques (PACT 2000)

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
On the Performance of Fetch Engines Running DSS Workloads

6th International Euro-Par Conference (EuroPar'2000)

C. Navarro, A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Fetch Engines and Databases

3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3)

C. Navarro, A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Semi-static Branch Prediction for Optimized Code Layouts

3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3)

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero

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