URL: https://ieeexplore.ieee.org/abstract/document/9251256
Authors: Jamet, Alexandre / Alavarez, Lluc / Jiménez, Daniel / Casas, Marc
Research Lines: Runtime aware architectures
Publication: Proceedings of the 2020 IEEE International Symposium on Workload Characterization (IISWC)
Palabras clave: Big Data, cache management, graph processing, micro-architecture, workload evaluation