Miquel Moreto

- MIQUEL MORETO
- Position: HIGH PERFORMANCE DOMAIN-SPECIFIC ARCHITECTURES GROUP MANAGER
- Computer Sciences - High Performance Domain-Specific Architectures
- email: miquel [dot] moreto [at] bsc [dot] es
- Tel: +34 934137994

Primary tabs

Mostrando 21 - 30 resultados de 104

2019

Optimizing computation-communication overlap in asynchronous task-based programs

Proceedings of the 24th Symposium on Principles and Practice of Parallel Programming - PPoPP '19

E. Castillo, N. Jain, M. Casas, M. Moreto, M. Schulz, R. Beivide, M. Valero, and A. Bhatele
On the maturity of parallel applications for asymmetric multi-core processors

Journal of Parallel and Distributed Computing

K. Chronaki, M. Moreto, M. Casas, A. Rico, R. M. Badia, E. Ayguadé, and M. Valero
Sampled Simulation of Task-Based Programs

IEEE Transactions on Computers

T.. Grass, T.. E. Carlson, A.. Rico, G.. Ceballos, E.. Ayguade, M. Casas, and M. Moreto

2018

Are Next-Generation HPC Systems Ready for Population-level Genomics Data Analytics?

Workshop on Accelerator Architecture in Computational Biology and Bioinformatics

C. Bulla, L. Alvarez, and M. Moreto
ChopStiX: Systematic Extraction of Code-Representative Microbenchmarks

2018 IEEE International Symposium on Workload Characterization (IISWC)

C. Bulla, L. Alvarez, M. Moreto, R. Bertran, A. Buyuktosunoglu, and P. Bose
Data Prefetching on In-order Processors

2018 International Conference on High Performance Computing & Simulation (HPCS)

C. Ortega, V. Garcia, M. Moreto, M. Casas, and R. Rusitoru
Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs

Proceedings of the 2018 International Conference on Supercomputing - ICS '18

L. Alvarez, M. Casas, J. Labarta, E. Ayguadé, M. Valero, and M. Moreto
Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies

Proceedings of the 2018 International Conference on Supercomputing - ICS '18

I. Sánchez-Barrera, M. Moreto, E. Ayguadé, J. Labarta, M. Valero, and M. Casas
Runtime-assisted Cache Coherence Deactivation in Task Parallel Programs

Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC)

P. Caheny, L. Alvarez, M. Valero, M. Moreto, and M. Casas
Stencil codes on a vector length agnostic architecture

Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques - PACT '18

A. Armejach, H. Caminal, J. M. Cebrián, R. González-Alberquilla, C. Adeniyi-Jones, M. Valero, M. Casas, and M. Moreto

Páginas