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Inici > Timing Effects of DDR Memory Systems in Hard Real-time Multicore Architectures: Issues and Solutions

Timing Effects of DDR Memory Systems in Hard Real-time Multicore Architectures: Issues and Solutions

URL:  http://doi.acm.org/10.1145/2435227.2435260

Authors: Paolieri, Marco / Quinones, Eduardo / Cazorla, Francisco

Publication: ACM Trans. Embed. Comput. Syst.

Place Published: New York, NY, USA

Volume / Number / Pagination: 12 / 1s / 64:1–64:26

Paraules clau: hard real-time, memory controller, multicore, SDRAM, wcet

Barcelona Supercomputing Center - Centro Nacional de Supercomputación
Source URL (retrieved on 18 des 2024 - 10:58): https://www.bsc.es/ca/research-and-development/publications/timing-effects-ddr-memory-systems-hard-real-time-multicore